1. Field of the Invention
The present invention relates to data processing units responsive to interrupt signals to carry out a corresponding interrupt routine.
2. Description of the Prior Art
In a data processing apparatus which is responsive to an interrupt signal to carry out a corresponding interrupt routine, variations in the time taken to respond to an interrupt (i.e. the time between the interrupt signal being asserted and when the first instruction of the corresponding interrupt routine is executed) can be problematic in real time systems. These problems may be particularly serious in relation to high priority interrupts, to which it is desirable that the data processing apparatus responds in a swift and predictable manner.
It is known that data processing apparatuses may use a stack based exception model when responding to an interrupt. In such models, on receipt of an exception or interrupt signal, the processing unit is configured to store a set of data values indicative of the current state of the processor (typically this being the contents of a set of registers within the processing unit) on a data stack. On completion of the interrupt routine triggered by the interrupt signal, the processing unit then retrieves the set of data values from the data stack, in order to continue program execution at the point where the interrupt signal was received. Such a stack based exception model may be atomic and un-interruptable, i.e the stacking/unstacking process must be wholly completed before the processing unit can perform any other activity. This has the advantage of preserving the coherency of the set of data values indicating the processor state, but may also worsen “interrupt jitter” by increasing the worst case interrupt response time. Alternatively, the stack based exception model may be interruptable, allowing a higher priority interrupt to disrupt an ongoing stacking/unstacking process, providing the necessary additional mechanisms to cope with the part-stacked/unstacked data stack. This may for example be carried out by allowing a higher priority interrupt to step in on a stacking process commenced by a lower priority interrupt, simply continuing that stacking process until the full set of data values has been transferred to the data stack and then commencing the interrupt routine corresponding to the higher priority interrupt. Since, relative to when the higher priority interrupt was received, the first instruction of the interrupt routine corresponding to the higher priority interrupt begins execution sooner than if that higher priority interrupt had been received in isolation, this worsens interrupt jitter by offering a lower than normal interrupt response time.
Accordingly, it would be desirable to provide a technique which enabled greater consistency in interrupt response times.